[TangerineSDR] Notes from PSWS / TangerineSDR call of 06-21-2021

[Tom McDermott]

Notes from PSWS / TangerineSDR call of 06-21-2021

1. Discussion on receiver ADC converter internal clock edge synchronization
input pin across different modules. Timing of this signal is pretty
critical, David M. requested that this capability not be eliminated. It
will require an active level translator from the FPGA 2.5 volt logic levels.
The SPI signals into / out of the ADC can use passive level clamping and
shifting (resistors and Schottky diodes) due to their slow speed.

- Tom, N5EG
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