[TangerineSDR] Notes from PSWS / TangerineSDR call of 06-21-2021

[Dr. Nathaniel A. Frissell Ph.D.]

Thank you, Tom.

The recording is uploading now and will be available later today at https://youtu.be/ENTPi9fEfwc and hamsci.org/telecons.

73 Nathaniel W2NAF

From: TangerineSDR <tangerinesdr-bounces at lists.tapr.org> On Behalf Of Tom McDermott via TangerineSDR
Sent: Monday, June 21, 2021 10:15 PM
To: TAPR TangerineSDR Modular Software Defined Radio <tangerinesdr at lists.tapr.org>
Cc: Tom McDermott <tom.n5eg at gmail.com>
Subject: [TangerineSDR] Notes from PSWS / TangerineSDR call of 06-21-2021


Notes from PSWS / TangerineSDR call of 06-21-2021

1. Discussion on receiver ADC converter internal clock edge synchronization input pin across different modules. Timing of this signal is pretty critical, David M. requested that this capability not be eliminated. It will require an active level translator from the FPGA 2.5 volt logic levels.
The SPI signals into / out of the ADC can use passive level clamping and shifting (resistors and Schottky diodes) due to their slow speed.

- Tom, N5EG



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