[TangerineSDR] Notes from PSWS / TangerineSDR call of 08-26-2019
tom.n5eg at gmail.com
Mon Aug 26 22:23:15 EDT 2019
Notes from PSWS / TangerineSDR call of 08-26-2019
1. Discussion of FPGA clocking scheme. Gold plated fingers are on the DE,
while the MEC connectors are on the RF modules.
2. Add analog input pin on CLM ICD for low cost VCXO control voltage input.
3. How to handle 4 receivers from a common clock module?
4. Is there some switch technology that can handle Dickie switching of
noise and receiver? What would the cost and 3rd order intermod performance
be? PIN diodes have problems below about 1-2 MHz.
5. Need cost estimates for DE and RF Modules.
6. Hardware unique serial number on every receiver?
What are the manufacturing implications? Can buy EPROMS and
One-Time-Programmable ROMS with unique serial numbers.
7. Can we fit a reset line on the receiver module? For shared I2C-SPI, do
we have enough chip select lines? We are out of connector pins.
-- Tom, N5EG
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