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<p class="MsoNormal">Thank you, Tom.<o:p></o:p></p>
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<p class="MsoNormal">The recording is uploading now and will be available later today at
<a href="https://youtu.be/ENTPi9fEfwc">https://youtu.be/ENTPi9fEfwc</a> and hamsci.org/telecons.<o:p></o:p></p>
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<p class="MsoNormal">73 Nathaniel W2NAF<o:p></o:p></p>
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<p class="MsoNormal"><b>From:</b> TangerineSDR <tangerinesdr-bounces@lists.tapr.org>
<b>On Behalf Of </b>Tom McDermott via TangerineSDR<br>
<b>Sent:</b> Monday, June 21, 2021 10:15 PM<br>
<b>To:</b> TAPR TangerineSDR Modular Software Defined Radio <tangerinesdr@lists.tapr.org><br>
<b>Cc:</b> Tom McDermott <tom.n5eg@gmail.com><br>
<b>Subject:</b> [TangerineSDR] Notes from PSWS / TangerineSDR call of 06-21-2021<o:p></o:p></p>
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<p class="MsoNormal">Notes from PSWS / TangerineSDR call of 06-21-2021<o:p></o:p></p>
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<p class="MsoNormal">1. Discussion on receiver ADC converter internal clock edge synchronization input pin across different modules. Timing of this signal is pretty critical, David M. requested that this capability not be eliminated. It will require an active
level translator from the FPGA 2.5 volt logic levels.<o:p></o:p></p>
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<p class="MsoNormal">The SPI signals into / out of the ADC can use passive level clamping and shifting (resistors and Schottky diodes) due to their slow speed.<o:p></o:p></p>
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<p class="MsoNormal">- Tom, N5EG<o:p></o:p></p>
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