[TangerineSDR] Notes from PSWS / TangerineSDR call of 01-20-2020

[Tom McDermott]

Notes from PSWS / TangerineSDR call of 01-20-2020

1. Tom to add on the Receiver module four 0603 zero-ohm resistors on the
FPGA_Clk_in and OSC_Clk_In diff pairs in order to allow choosing which
clock drives the receiver module.

2. Dave W. to send Scotty a schematic of the magnetometer & PMOD connection
to make sure that the PMOD pins are defined correctly.

3. Scotty would prefer a separate UDP control stream, one per virtual
receiver. Each control stream will set characteristics of its associated
channel: The center frequency, width, datarate (probably synonymous with
width), which physical ADC channel, format of the channel (IQIQ, IIQQ,
I0Q0I1Q1, etc). Original request is 8 virtual receiver channels per
physical channel (i.e. total of 16 virtual channels for one dual-ADC
receiver board).

-- Tom, N5EG
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