[TangerineSDR] [hamsci-grape] Re: 3-Channel VLF SDR Backend System

Jonathan emuman100 at gmail.com
Tue Aug 15 12:50:11 EDT 2023

Hi John,

Did you take measurements of the PPS  and clock accuracy? How is the 8 kHz
sample clock synthesized?

The Audio Injector Octo uses a crystal oscillator, but like in the previous
email thread about timing, vlfrx-tools is constantly making measurements
and calibrating out the delay, then realigning each sample according to
that series of calibrations and alignment of the centroid of an RC
network-shaped PPS. I manually insert a calibration value consisting of the
time between the rising edge of the rectangular pulse and the centroid of
the RC network-shaped pulse, giving me similar PPS accuracy as you have


On Mon, Aug 14, 2023 at 2:44 PM John Gibbons <jcg66 at case.edu> wrote:

> Jonathan,
> The absolute accuracy of the 1PPS synchronization lies exactly between 1-2
> sync clock cycles (crossing over clock domains requires this to prevent
> metastability - you must do this as well!)
> so my 1PPS is always between 125-250 nSec (8 MHz clk) from the 50 nSec
> window that the UBLOX gives me for absolute timing of the 1PPS signal.
> The derived sample clock, however, is deadly accurate as it is also
> derived from the UBLOX freq output so it will easily hold 1x10^-10 accuracy
> and on an 8 KHz sample clock it guarantees me to be within 12.5 aSec (yes
> 10^-15 sec).  Since I presume you're using the on board clock for your A/D
> card you will be at least 4 orders of magnitude worse as quartz xtals (or
> even worse a resonator!) are not so good (not to mention temp drift that
> will eat you alive...).
> The sample clock is very important as it determines your A/D sample freq
> hence directly affects any timing / frequency measurements you extract from
> your data.
> For us it directly affects the freq measurement of the carrier freq and
> needs to be pretty darn good (12.5 aSec is pretty respectable).
> What is your freq ref standard for the A/D sample clock?  Is it GPS DO'd?
> Is it synced to the 1PPS?
> John N8OBJ
> On Mon, Aug 14, 2023 at 12:13 PM Jonathan <emuman100 at gmail.com> wrote:
>> John,
>> Did you take measurements of the sampling and timestamping accuracy of
>> the Grape 2? I don't believe you included it in the other email.
>> Jonathan
>> On Mon, Aug 14, 2023 at 11:21 AM John Gibbons <jcg66 at case.edu> wrote:
>>> That has already been designed and built and hardware tested (with
>>> better timing for data sampling) - it's called the Grape 2
>>> John N8OBJ
>>> On Mon, Aug 14, 2023 at 9:57 AM Jonathan <emuman100 at gmail.com> wrote:
>>>> My apologies, the pictures did not attach inline. The attachments are
>>>> all in order of what I describe.
>>>> Jonathan
>>>> KC3EEY
>>>> On Mon, Aug 14, 2023 at 6:20 AM Jonathan <emuman100 at gmail.com> wrote:
>>>>> I have been working on a 3-channel VLF backend system similar to the
>>>>> single channel system I built in 2020. It's based on a Raspberry Pi 3,
>>>>> Audio Injector Octo Soundcard, Trimble Resolution SMTx GPS timing receiver,
>>>>> and VLF preamp interface board and power distribution. It's designed to
>>>>> capture VLF spectrum from an E-field receiver and an orthogonal loop dual
>>>>> channel H-field receiver for triple axis reception of the VLF band. With
>>>>> it, bearing can be determined and the loops can be synthesized for any
>>>>> bearing based on how the loop signals are mixed. This provides additional
>>>>> analysis of VLF signals using the powerful vlfrx-tools software. Everything
>>>>> in mounted in a Hammond dicast aluminum enclosure. In the center is the
>>>>> Raspberry Pi 3B, Audio Injector Octo Soundcard with audio breakout board,
>>>>> and TTL<>RS232 adapter for the serial console. On the left are power,
>>>>> capture, and timing status indicator LEDs as well as a safe shutdown button
>>>>> to safely unmount the data USB drive. On the right is the Trimble
>>>>> Resolution SMTx and interface board. On the bottom is the VLF receiver
>>>>> interface board.
>>>>> This is the Pi 3B with Audio Injector Octo soundcard. It has 6 audio
>>>>> inputs and can sample up to 96 kHz. The audio breakout board breaks out the
>>>>> audio inputs to RCA jacks, which I removed, for a direct solder connection.
>>>>> The PPS from the GPS gets get through a potentiometer for adjustment to 80%
>>>>> of the soundcard’s full scale. I will be feeding it through an RC network
>>>>> to shape the 125 us pulse. The PPS is also connected to a GPIO pin for use
>>>>> with the ppsgpio driver, GPS Daemon, and ntp and functions as a networked
>>>>> stratum 1 time server as well. Data is stored on a 512 MB USB drive. The
>>>>> console port is accessible via TTL<>RS232 adapter (in blue heat shrink) for
>>>>> complete headless operation, especially when the network is not available.
>>>>> Both the Ethernet and RS232 are connected to RJ45 bulkhead couplers for
>>>>> panel jack connection. The indicator LEDs, shutdown button, console port,
>>>>> and GPIO PPS all connect through a 40-pin female header.
>>>>> The GPS is a Trimble Resolution SMTx GPS timing receiver. I used it
>>>>> because it was cheap and what I had on hand, but still performs well for an
>>>>> older model of the Trimble/Protempis GNSS timing receiver line. The PPS
>>>>> time pulse width is 125 us. It’s powered using the handy PPS Piggy
>>>>> interface board for Trimble/Protempis receivers. The antenna is connected
>>>>> through an SMA to SMB pigtail with bulkhead SMA jack. The other hole in the
>>>>> enclosure is for the Raspberry Pi WiFi antenna jack which I will add later.
>>>>> The indicator LEDs are panel mounted as well as the safe shutdown
>>>>> button. These provide an indicator for power, soundcard capture, and GPS
>>>>> timing, with the later two controlled by GPIO pins and series resistors.
>>>>> The safe shutdown button will issue “shutdown -h now” when pressed for
>>>>> longer than 3 seconds to safely unmount the USB drive if no network or
>>>>> console access is available. Data will constantly be written to the USB
>>>>> drive during normal operation in bursts. The USB drive is ext2 fornated.
>>>>> The LED indicators and safe shutdown button are monitored via script.
>>>>> Lastly, this is the VLF receiver interface board. It provides power to
>>>>> the Pi and GPS receiver using an adjustable 3A DC-DC converter set to 5.1V.
>>>>> Power to the E-field and H-field VLF receiver channels is through 24V
>>>>> isolated DC-DC converters. Main power comes in via 12V unregulated wallwart
>>>>> and drives both the adjustable DC-DC converter and the isolated DC-DC
>>>>> converters. The VLF receiver channels also have audio isolation
>>>>> transformers to maintain isolation between the backend system and VLF
>>>>> preamp and connect to the audio inputs on the audio breakout board. Both
>>>>> the power and signal paths have 10M bleeder resistors to bleed off any
>>>>> excess charge on the feedline as well as gas discharge arrestors for surge
>>>>> protection. The feedline is shielded cat5 or cat 6 cable pairs and connect
>>>>> to the green screw terminals. The isolated DC-DC converters are plugged
>>>>> into pin sockets and are removable in case the feedline is too long and 48V
>>>>> DC-DC converters are used to maintain the voltage at the end of the
>>>>> feedline due to the voltage drop of a long feedline. The board also
>>>>> provides a connection to power LED indicator as well.
>>>>> My next step is to fine tune the shaped PPS pulse for more accurate
>>>>> timing. Once complete, I will start work on the dual channel H-field
>>>>> receiver.
>>>>> Jonathan
>>>>> KC3EEY
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