[TangerineSDR] Notes from PSWS / TangerineSDR call of 03-08-2021
tom.n5eg at gmail.com
Mon Mar 8 22:49:12 EST 2021
Notes from PSWS / TangerineSDR call of 03-08-2021
1. The meeting time changes next week to account for Daylight Saving Time.
Local time stays the same (6 PM PDT / 9 PM EDT) except for those who don't
go on DST. Starts 0100Z Tuesday AM UTC.
2. Welcome to new attendee(s): Cuomg Gaming, student learning about FPGA
3. Grape 1 documentation available at:
4. Joe W7LUX working on a phase noise measuring setup that should be able
to resolve down to the PSWS project requirements.
5. Jonathan mentioned vlfrx tools for analyzing VLF signals:
6. Discussion on the DE-LH protocol: how can the host identify how the
data engine is equipped, which modules are installed, what FPGA code and
version is loaded, etc? We need to refine the existing document. Dave was
asked to propose additions to the discovery response that contain the FPGA
load name, revision, module equippage, Port_A, etc. More detail would then
be handled by FPGA-load-dependent responses (different protocol document).
7. David, Scotty, and Tom to work offline on receiver ADC to DE electrical
interface issues: LVDS vs. CMOS.
-- Tom, N5EG
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