[TangerineSDR] Last test on Silicon Labs synthesizer cip / eval board.

Tom McDermott tom.n5eg at gmail.com
Tue Apr 30 20:17:33 EDT 2019


I finished the last test planned for the silicon Labs board.  This test
turned on all 4 outputs
from the board, set them 1 Hertz apart from each other, and turned off the
OUT0 jitter
minimization, allowing the dividers to be used as needed for all four
outputs.

After a 12 hour run, the ADEV of OUT0 is the same as when only one output
was turned on (OUT0)
and it was set for jitter minimization at the exclusion of others.  I won't
post a chart as
it is just two straight lines on top of each other.

Overall I'm quite impressed with the performance of the SI chip / eval
board.  It appears that
it could be a good candidate to generate the clocks for the SDR - ADC
clock, FPGA clock, etc.)
I was only able to find one condition where it degraded, and we probably
should be able to
dodge that by avoiding certain ratios when we select the ADC and FPGA clock
rates.

-- Tom, N5EG
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