[TangerineSDR] Just joined and some comments

[Tom McDermott]

Hi Lyle,  welcome to the list !

I started out asking the same questions about 9 months ago.  Evaluation
of a few units was disappointing for the project needs, especially Red
Pitaya.

John Ackermann N8UR did an evaluation of about 25-30 units, and put together
a slide deck.  Perhaps we can persuade him to upload it to the mail list.

One thing we have found so far on virtually all the available SDR units is
very
poor ADC clock stability. Even with externally GPSDO referenced clocks.
We are trying to time stamp the samples within +/- 50 nanosecond accuracy,
which a modern GPSDO should be able to achieve.  What we have seen on
the SDRs looked at is the ADC clock drifting way more than that even when
locked to
a high accuracy oscillator. This is due to several causes, one is the use
of phase
locked loops in deriving ADC clock from reference clock. The FPGA based
loops
so far have worked remarkably poorly.

We also need to calibrate amplitude, and whilst an easier problem, it's not
built into the receivers looked at.

I would still hope it would be possible to use off-the-shelf hardware, but
nothing
suitable has shown up via UPS so far.

-- Tom, N5EG










On Fri, Apr 26, 2019 at 9:07 AM Lyle Johnson via TangerineSDR <
tangerinesdr at lists.tapr.org> wrote:

> Hello Scotty, Dan and Tom!
>
> Still digesting the preliminary document.  I see lots of IO...
>
> I also see references to PSWS which seems to be Personal Science Work
> Station.  Not sure what this is intended to be.
>
> I also recall some interest in a "space weather station" but have been
> out of the loop for too long.
>
> The TangerineSDR Data Engine seems to be a general purpose FPGA
> development board with lots of specialized IO.
>
> I am unclear as to what specific problems this project is attempting to
> solve, or what peripheral board(s) might be needed to solve the problem
> set that is driving this development.  Are such boards already existing
> (hence the large set of various standard IO interfaces) or do many/most
> of them still need to be designed -- and if so how does that play out in
> the overall scheme of things?
>
> TAPR's early history with general purpose solutions not aimed at solving
> a particular (perceived) need in the community in general meant a lot of
> development effort by one to five individuals to create something that
> was only adopted by a few tens (METCON comes to mind).
>
> Does a board like the Red Pitaya - especially if it were to have a
> TAPR-sourced "IO expander" - already solve many or most of the problems
> that this board attempts to solve?  Or the new Red Pitaya-SDR with
> bigger FPGA, better ADC, 50-ohm front end, lower noise floor, etc but at
> $500 (fast 16 bit ADCs and 14-bit DACs) instead of $200 (10-bit fast
> ADCs/DACs) or $300 (fast 14-bit ADCs/DACs), solve the problem(s)?
>
> -Lyle KK7P
>
>
> --
> TangerineSDR mailing list
> TangerineSDR at lists.tapr.org
> http://lists.tapr.org/mailman/listinfo/tangerinesdr_lists.tapr.org
>
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