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<p class="MsoNormal">Thank you, Tom. The video will be available on hamsci.org/telecons later today.<o:p></o:p></p>
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<p class="MsoNormal">73 Nathaniel W2NAF<o:p></o:p></p>
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<p class="MsoNormal"><b>From:</b> TangerineSDR <tangerinesdr-bounces@lists.tapr.org>
<b>On Behalf Of </b>Tom McDermott via TangerineSDR<br>
<b>Sent:</b> Monday, March 8, 2021 10:49 PM<br>
<b>To:</b> TAPR TangerineSDR Modular Software Defined Radio <tangerinesdr@lists.tapr.org><br>
<b>Cc:</b> Tom McDermott <tom.n5eg@gmail.com><br>
<b>Subject:</b> [TangerineSDR] Notes from PSWS / TangerineSDR call of 03-08-2021<o:p></o:p></p>
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<p class="MsoNormal">Notes from PSWS / TangerineSDR call of 03-08-2021<o:p></o:p></p>
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<p class="MsoNormal">1. The meeting time changes next week to account for Daylight Saving Time. Local time stays the same (6 PM PDT / 9 PM EDT) except for those who don't go on DST. Starts 0100Z Tuesday AM UTC.<o:p></o:p></p>
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<p class="MsoNormal">2. Welcome to new attendee(s): Cuomg Gaming, student learning about FPGA and coding.<o:p></o:p></p>
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<p class="MsoNormal">3. Grape 1 documentation available at:<o:p></o:p></p>
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<p class="MsoNormal"><a href="https://nam10.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2FHamSCI%2FPSWS_Documentation%2Ftree%2Fmaster%2FGrape_Gen1_PSWS&data=04%7C01%7Cnathaniel.frissell%40scranton.edu%7C66d22e6448224243d4d508d8e2af81c3%7Ca8edc49a41f14c699768a7f6d7c3b8c3%7C0%7C0%7C637508590721128708%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=CvAktLV%2FwPABy%2BjGKSLSyjMbs1Lntqu4Ev9rZ%2FXfKkU%3D&reserved=0">https://github.com/HamSCI/PSWS_Documentation/tree/master/Grape_Gen1_PSWS</a><o:p></o:p></p>
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<p class="MsoNormal">4. Joe W7LUX working on a phase noise measuring setup that should be able to resolve down to the PSWS project requirements.<o:p></o:p></p>
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<p class="MsoNormal">5. Jonathan mentioned vlfrx tools for analyzing VLF signals:<o:p></o:p></p>
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<p class="MsoNormal"><a href="https://nam10.safelinks.protection.outlook.com/?url=http%3A%2F%2Fabelian.org%2Fvlfrx-tools%2F&data=04%7C01%7Cnathaniel.frissell%40scranton.edu%7C66d22e6448224243d4d508d8e2af81c3%7Ca8edc49a41f14c699768a7f6d7c3b8c3%7C0%7C0%7C637508590721128708%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=NGHFaxj7P%2BGGFn98Jh65KYr2STMDMzLGMVGxLZHD%2BsA%3D&reserved=0">http://abelian.org/vlfrx-tools/</a><o:p></o:p></p>
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<p class="MsoNormal">6. Discussion on the DE-LH protocol: how can the host identify how the data engine is equipped, which modules are installed, what FPGA code and version is loaded, etc? We need to refine the existing document. Dave was asked to propose
additions to the discovery response that contain the FPGA load name, revision, module equippage, Port_A, etc. More detail would then be handled by FPGA-load-dependent responses (different protocol document).<o:p></o:p></p>
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<p class="MsoNormal">7. David, Scotty, and Tom to work offline on receiver ADC to DE electrical interface issues: LVDS vs. CMOS.<o:p></o:p></p>
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<p class="MsoNormal">-- Tom, N5EG<o:p></o:p></p>
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