[TangerineSDR] GPSDO Thoughts

[John Ackermann. N8UR]

Scotty, I just had a thought -- would it be feasible to breadboard the 122.88 PLL circuit with a cheap FPGA so we could do some tests to optimize the loop design (both hardware and VHDL)?  It would be interestimg to test filter bandwidth, divisor ratios, etc.

On Sep 29, 2019, 9:41 PM, at 9:41 PM, Scotty Cowling via TangerineSDR <tangerinesdr at lists.tapr.org> wrote:
>Hi John,
>
>So does it look like the Crystek oscillator with a 4-way output buffer 
>is the best solution for the stand-alone (no CKM) version of the DE?
>
>The oscillator is about $15 in quantity, with the 4-way buffer (Si Labs
>
>SI53341-B-GM) at $1.17 in quantity. This seems to be the cheapest way
>to 
>get the best non-GPSDO performance, and if we can get the Hermes method
>
>to work we could use it as the basis of the GPSDO CKM, couldn't we?
>
>73,
>Scotty WA2DFI
>
>On 2019-09-29 16:27, John Ackermann N8UR via TangerineSDR wrote:
>> Thanks for that Lyle.  The 570 is a neat device, but as you said is
>> stand-alone.
>>
>> We were looking at the SiLabs 543x series clock
>generator/cleanup/driver
>> chips which are basically complex synthesizers with virtually
>arbitrary
>> input frequency and multiple independent outputs settable to anything
>> from 1 Hz to over 1 GHz.  The niftiest versions use a 48 MHz crystal
>> oscillator as a phase noise cleanup and can get to a pretty
>impressive
>> noise floor (something around -150 at 144 MHz) but not as good as the
>> Crystek 122.88 MHz VCXO.
>>
>> But they're in the $13-18 price range (depending on type), have some
>> fiddly layout requirements (want a six layer board), and require
>> ultra-low-noise regulators at significant current, so as much as I
>love
>> the idea, I'm not sure it's the right choice, at least for a
>first-out
>> version.
>>
>> For just a 122.88 output, the Crystek with a four-way output buffer
>is
>> cheaper and cleaner.  And we've learned what caused the PLL
>performance
>> problem in the Hermes-derived boards, so hopefully can avoid that
>this
>> time around.
>>
>> 73,
>> John
>> ----
>>
>> On 9/29/19 6:27 PM, Lyle Johnson wrote:
>>> We used the Si570 in the K3S and KX3 synthesizers.  Excellent noise
>characteristics but can’t be slaved to an external reference.  We use a
>SiLabs synth in the KX2 that can use an external reference but noise
>performance is much worse.
>>>
>>> FWIW,  Lyle KK7P
>>>
>>> Sent from my iPhone
>>>
>>>> On Sep 29, 2019, at 2:39 PM, John Ackermann N8UR via TangerineSDR
><tangerinesdr at lists.tapr.org> wrote:
>>>>
>>>> To the TangerineSDR list --
>>>>
>>>> I've spent the week since DCC thinking about GPSDO questions and
>getting
>>>> things in place to do some experiments.  I was going to put
>together a
>>>> starting-point paper and send it to you and a few time/gps-nuts but
>>>> thought it was better to get some data first.
>>>>
>>>> In quick summary:
>>>>
>>>> A GPSDO is nothing more than a crystal oscillator ("XO") with an
>EFC
>>>> input that is steered to frequency by reference to the precise time
>>>> available from a GPS receiver, usually in the form of a
>pulse-per-second
>>>> signal.  The crystal oscillator can have excellent short-term
>stability,
>>>> but will drift (age) over time and is subject to environmental
>>>> variables, particularly temperature.  The GPS system has excellent
>long
>>>> term stability and accuracy, ultimately tracking USNO(UTC) but
>short
>>>> term usually requires long averaging times to reach that
>performance.
>>>>
>>>> The task of the GPS designer, given the known performance of the XO
>and
>>>> the GPS constellation, is to optimize the control loop to extract
>the
>>>> best of both.
>>>>
>>>> A better XO allows the time constant of the control loop to be
>longer.
>>>> A quieter GPS implementation allows the time constant of the
>control
>>>> loop to be shorter.  What's of interest to me is that a shorter
>control
>>>> loop implies lower performance requirements on the XO, and that
>might
>>>> result in a way to lower overall GPSDO cost.
>>>>
>>>> This wouldn't be very interesting except that there are now some
>low
>>>> cost GPS receiver modules available that might -- maybe, perhaps,
>>>> possibly -- provide a lower-noise GPS time reference.  u-Blox
>>>> (https://www.u-Blox.com) has released a bewildering variety of
>>>> navigation and timing modules with varying capabilities.  I've
>attached
>>>> a table that I put together by extracting data from the u-Blox web
>site.
>>>>
>>>> I'll soon have my hands on five of these modules with different
>>>> capabilities (and price points).  Once I've had a chance to take
>some
>>>> initial measurements, and verify some specs that aren't clear from
>the
>>>> documentation, I'll provide an updated report that might serve as
>the
>>>> basis for some design discussions.
>>>>
>>>> I'm also reaching out to a few friends in the time-nuts world to
>get
>>>> some recommendations for readily available 10 MHz XOs at a couple
>of
>>>> different price/performance points that we can at least use to
>provide
>>>> cost information.
>>>>
>>>> Finally, I'm thinking about whether the SiLabs frequency
>synthesizer
>>>> chip is the most cost-effective way to get the low-phase-noise
>122.88
>>>> MHz performance we need.  It might be cheaper, and better, to use
>the
>>>> Hermes scheme, where a very low jitter 122.88 VCXO is locked to the
>10
>>>> MHz reference -- provided we fix the known problem with the Hermes
>>>> implementation.  The synthesizer offers flexibility, but I think
>its
>>>> cost (with required supporting components) will be greater than the
>>>> Crystek 122.88 oscillator module, and its phase noise performance
>not
>>>> quite as good.
>>>>
>>>> Anyway, more to come.
>>>>
>>>> 73,
>>>> John
>>>>
>>>>
>>>>
>>>> <uBlox_GPS_Comparison_v2.pdf>
>>>> -- 
>>>> TangerineSDR mailing list
>>>> TangerineSDR at lists.tapr.org
>>>> http://lists.tapr.org/mailman/listinfo/tangerinesdr_lists.tapr.org
>>
>
>
>
>
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