[TangerineSDR] TangerineSDR Board Sizes and Mock-up

[John Ackermann N8UR]

The "magic" I'm working on is whether we can use real time corrections
via internet or another mechanism to reduce the GPS noise.  It appears
we may be able to reduce the ADEV by an order of magnitude.  If we do
that, the loop time constant can be shorter which would allow for a
cheaper oscillator.  But there's still a bunch of testing to do to
confirm that and figure out a final design.

On 9/21/19 5:00 PM, Rick - W2GPS wrote:
> John,
> 
> I noticed the various layout examples in the SiLabs 53xx documentation but I
> did not notice the 6-layer requirement. At present, the board stack is
> 4-layer, 80mm (0.31") thick to match the M.2 specification.  It is set up to
> match the stack-up requirements for standard configuration from low cost
> board houses like 4pcb.com. I just checked and it will be easy to change
> this to 6-layer, 80mm (0.31") thick board while staying within their low
> cost board structure.
> 
> I will need to find a low cost TCXO for the base configuration. The OCXO I
> show is well over $100 in 50-piece quantity. It can get to twice that if
> over specified.  I hope the footprints can be overlaid to save room.
> 
> The board size will be a challenge, I'm sure.
> 
> Rick
> W2GPS
> 
> 
> -----Original Message-----
> From: TangerineSDR <tangerinesdr-bounces at lists.tapr.org> On Behalf Of John
> Ackermann N8UR via TangerineSDR
> Sent: September 21, 2019 4:43 PM
> To: tangerinesdr at lists.tapr.org
> Cc: John Ackermann N8UR <jra at febo.com>
> Subject: Re: [TangerineSDR] TangerineSDR Board Sizes and Mock-up
> 
> Thanks, Rick.  I've finally started paying attention and have been thinking
> about some unique GPSDO ideas.  They may change the physical parts a bit but
> we're a long way from having anything finalized.
> 
> I think we've concluded that the RF output from the M8F module is not
> acceptable for RF use -- it has a very ugly dither pattern so we will likely
> need a external (TC)(OC)XO and DAC no matter what architecture we end up
> with.
> 
> One thing to note: the SiLabs 53xx chip wants a 6 layer board and also has
> some fairly funky layout requirements; a bunch of this is due to crosstalk
> reduction, and the 48 MHz crystal used as the cleanup oscillator.  The chip
> is physically small, but pretty complex to lay out.
> 
> 73,
> John
> 
> On 9/21/19 4:24 PM, Rick - W2GPS via TangerineSDR wrote:
>> All,
>>
>> I have been working on the clock module to see if the proposed size for
> the clock module is reasonable. Attached is a 3D top view showing major
> components. Not shown is the D/A to drive the OCXO and various minor
> components. These may wind up on the bottom of the board.
>>
>> Rick
>> W2GPS
>>
>> -----Original Message-----
>> From: TangerineSDR <tangerinesdr-bounces at lists.tapr.org> On Behalf Of 
>> Scotty Cowling via TangerineSDR
>> Sent: September 17, 2019 11:50 AM
>> To: TAPR TangerineSDR Modular Software Defined Radio 
>> <tangerinesdr at lists.tapr.org>
>> Cc: Scotty Cowling <scotty at tonks.com>
>> Subject: [TangerineSDR] TangerineSDR Board Sizes and Mock-up
>>
>> Here is a sneak preview of part of the TangerineSDR talk I will be giving
> at DCC on Saturday.
>>
>> Rick, this should be enough information on the PCB sizes to figure out if
> we have enough room or not.
>>
>> The CKM can be extended downward and/or to the right (when looking at the
> assembly with the RPi I/O connector on top). We may have to make the DE
> board larger anyway, if our CAD guy needs more routing room.
>>
>> 73,
>> Scotty WA2DFI
>>
>>
> 
> 
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