[TangerineSDR] PSWS System Specification preliminary Ver 0.1

Fri May 3 10:52:27 EDT 2019

For PSWS, I believe that the data has to flow thru the SBC, for a number of reasons (e.g., for queuing since few people have the internet bandwidth to upload directly; to handle sign-in credentials, etc.); however, if the idea is to design a multi-application radio, perhaps there could be an option to directly upload to something else (i.e., another instrument on the local network). Just a thought.

From: TangerineSDR <tangerinesdr-bounces at lists.tapr.org> On Behalf Of Scotty Cowling via TangerineSDR
Sent: Friday, May 3, 2019 9:09 AM
To: TAPR TangerineSDR Modular Software Defined Radio <tangerinesdr at lists.tapr.org>
Cc: Scotty Cowling <scotty at tonks.com>
Subject: Re: [TangerineSDR] PSWS System Specification preliminary Ver 0.1

Hi Tom,

Regarding the clocks, it seems that the AD5344 addresses this problem with the cross-point switch and synchronous dividers.

We can feed two outputs with one synthesizer if we like, for a fixed (and very small) phase offset. Routing one clock output to two RF Modules is problematic, especially with LVDS outputs. Wouldn't this work?

Alternatively, we could put a clock distribution chip on the DE to take one Clock Module output and distribute it to FPGA, RFM1 and RFM2, but then we lose the capability to clock the RFMs at different frequencies (for example, when one is a TX and one is an RX).

One thing to keep in mind is that the FPGA has multiple clock inputs, so we can route one from each RFM, one from the Clock Module and one from a local oscillator and let the FPGA code decide which one to use. Of course, we would have to either let the FPGA generate the RFM clocks or route multiple clocks to each RFM to clock the ADCs directly. The reason I bring this up is that I want to use an on-board inexpensive oscillator (and no Clock Module at all) as the inexpensive, entry-level SDR. No, the performance would not be as good. But the cost would be much lower than with any clock module, and it would be selectable by simply loading the FPGA with a different image and unplugging the Clock Module.

The section 7 comment was not intended to dictate a data flow path. I just wanted to show that we need (and will have) two GbE ports to use that path in case we want to handle data in this way (for example, if the SBC cannot keep up). We can word it in whatever way makes it clear that we can do it either way. Isn't your description implementation specific also (i.e., data flows through the SBC)?

Maybe for PSWS, the data has to flow through the SBC? That is the impression I got, and I am not sure we want to restrict the architecture that way, but we could if that is our intent.

73,
Scotty WA2DFI

On 2019-05-03 04:09, Tom McDermott wrote:
Thanks for the good comments, Scotty !

Section 3:  the ADC clocks MUST come from the same one synthesizer output. If they
come from two different outputs there is a big problem...

The clocks to the two ADCs  must be (and remain) phase coherent. If the ADC clocks come
from different outputs of the synthesizer, then each time the synthesizer starts, there could
be any phase difference between the two. Further they could drift back and forth relative to one another
a little bit because of the way synthesizers work.  Thus the phase between them under
the best case would be +/- 180 degrees.  At 30 MHz that would represent +/- 45 degrees.  This
means that the baseband sampled signal at 30 MHz would also have an unknown phase
difference of +/- 45 degrees.  That completely wrecks the ability to discriminate polarization.

There can be a difference in phase between the two ADC clocks, but it must remain constant over time.
Any difference will be calibrated out when the antennas and feedlines are calibrated for phase delay.
But then the phase differences cannot change.  The only way I see to do that is to have one
synthesizer output that is distributed to the two ADC clocks.  If the ADCs are on different modules
then one clock signal has to be routed to the two of them in some manner (parallel, daisy-chained, etc.)
Maybe there is some other way but it's difficult to see.

This is one of those things that makes phase coherent receivers very difficult, and why off-the-shelf units
have to be carefully evaluated, as virtually none of the ones I've seen address this problem properly.
It's the Radio Astronomy problem.

Section 7:  The spec attempts to be implementation-non-specific.  Forcing a particular method
to distribute Ethernet data may eliminate all other potential solutions.  The approach you outline
is a really good and elegant solution, but the spec should not mandate it (it should allow it).

Section 8:  great comment.  I will restructure as you outline.

-- Tom, N5EG

On Thu, May 2, 2019 at 5:27 PM Scotty Cowling via TangerineSDR <tangerinesdr at lists.tapr.org<mailto:tangerinesdr at lists.tapr.org>> wrote:
Hi Tom,

Here are my comments on your excellent document.

73,
Scotty WA2DFI

Notes on PSWS Specification V 0.1 5 May 2019

Section 3.0
Clock module will have 4 *programmable clock* outputs:
1. FPGA
2. RF Module #1
3. RF Module #2
4. High-speed Reference Clock

In addition, two more outputs:
5. 1 PPS timing
6. 10MHz fixed reference

Clock outputs should be differential LVDS. Single ended clocks will be
too noisy, especially across a connector boundary.

The FPGA should not provide the ADC clocks, they should come directly
from the clock module. The ADC may supply a source-synchronous data
clock to the FPGA.

Section 4.0
Magnetometer interface can be I2C, SPI, serial UART or RS-485.

The magnetometer will almost certainly need to be remotely mounted. In
this case, RS-485 is recommended. We can specify two-wires for
communictions and two wires for power (typically 5V).

Section 5.0
It is not immediately clear that *each* RF Module has two synchronous
channels.

Note that the *pluggable filter* can be bypassed with a jumper, making
it optional. Maybe call it "optional pluggable filter".

Section 6.
The DE shall also be capable of sourcing or sinking UDP data streams
to/from any IP address, under direction of the host processor.

The DE will have a three-port GbE switch, connecting the FPGA, host PC
and external network. How do you want to explain this?

Section 7.0
Processing the stream from the DE is optional, since it may not be able
to process this much data. The metadata tasks will fall to the DE in
this case.

The host will not always transmit the data to the central server. The
host may direct the DE to stream data directly to the central server if
it cannot process the volume or rate of data.

Section 8.
I have been using "Command and Control Protocol" for the protocol used
between the central server and the host PC. I have been using "Local SDR
Protocol" for the protocol between the host PC and the DE.

We could use "Remote Command and Control", or "RCC" for the
host<-->central server communications, and "Local Command and Control"
or "LCC" for host<-->DE communications. Whatever we use, we should
define it.

The Remote Command and Control section seems to be missing (although you
refer to it once in section 10). Even though we don't know what the
protocol    is, I think it should be mentioned (as defined an a separate
document?)

I think we need to make a clear distinction between Remote C&C and Local
SDR C&C. We will need security and maybe encryption on the Remote C&C,
but not so much on the Local SDR protocol.

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